It is desirable to reduce the size of known SRAM cells in order to reduce the overall size of integrated circuits and to improve circuit performance.
FIG. 1 is a schematic illustration of a prior art SRAM cell 10 having a contact bar providing an electrical strap 12 between the polycrystalline gates of two transistor devices (M1, M2) and the drain of a further transistor device (M4). The contact bar allows a reduction in the SRAM cell size to be made.
However, the introduction of the contact bar presents a number of process-related issues including a smaller process window for contact etch and a more complex optical proximity correction (OPC) model for the lithography process.
This is at least in part because in order to form the contact bar, a trench must be formed through an interlayer dielectric (ILD) layer overlying the transistor devices. Once the trench has been formed, a conducting material is deposited in the trench to form the contact bar.
One of the problems associated with the fabrication of SRAM cells having such a contact bar is that of ‘punch through’ due to contact over etch. ‘Punch through’ due to contact over etch refers to the situation in which an etch step results in a portion of a layer being etched that should not have been etched.
FIG. 2 shows a cross-sectional schematic diagram of a structure 50 after an etch process has been performed to remove a portion of ILD layer 60 thereby to expose a gate contact element 54 and a drain contact element 56. The gate and drain contact elements 54, 56 are formed from a metal silicide. The ILD layer may be formed from tetraethyl orthosilicate (TEOS), borophosphosilicate glass (BPSG) or any other suitable ILD material.
As can be seen in FIG. 2, region ‘A’ (at the interface between the ILD layer 60 and a shallow trench isolation (STI) region 51) is not provided with metal silicide. Consequently, it is difficult to terminate the etch process in region A at the stage when both the gate contact element 54, the drain contact element 56 and the STI region 51 are exposed without etching at least a portion of STI region 58. In other words, it is difficult to avoid ‘punch through’ during the etching process, thereby resulting in etching of a portion of STI region 58. Punch through is undesirable since it can result in bitline failure.
In view of the foregoing, it is desirable to provide memory cells with improved circuit performance.